1. Field of the Invention
The present invention generally relates to a semiconductor device having a SOI (silicon on insulator) substrate including a semiconductor layer, on which a desired element is formed, disposed on an insulating layer which is disposed on a conductive support substrate. More specifically, the present invention relates to a semiconductor device which is a thin type, has a high breakdown voltage, and is effectively applied to a flat type display device such as a plasma display device (hereinafter referred to as a PDP device) or an electroluminescence display device (hereinafter referred to as an EL device). The present application is based on Japanese Patent Application No. 363055/2000, which is incorporated herein by reference.
2. Description of the Related Art
With respect to a flat type display device such as the PDP device or the EL device, in order to realize miniaturization, thinness, reduce power consumption or the like, a high breakdown voltage semiconductor device is used in many cases. In particular, in the case of reduced consumption power by utilizing components having low consumption power including a semiconductor device to be used, in order to suppress the consumption of reactive power by charging and discharging a large stray capacitor necessarily included in the semiconductor device structure, a power recovery circuit is provided to reduce the consumption power of the display device.
FIGS. 1A and 1B show explanatory views of a low power driver device in a plasma display described in Japanese Patent No. 2770657. With reference to FIG. 1A, a low power driver device (power recovery circuit) 600 includes a capacitor CR having a sufficiently larger capacitance than a load capacitor CL, a p-channel type field effect transistor (hereinafter referred to as a pMOS) 611 and a diode D1, which function as a switch for charging CL from CR, an n-channel type field effect transistor (hereinafter referred to as an nMOS) 621 and a diode D2, which function as a switch for discharging CL, an inductor L1 which forms a resonant circuit together with CL at charge and discharge and recovers reactive power, a pMOS 612 to maintain an output at a voltage V0, and an nMOS 622 to maintain an output at a ground potential. The load capacitor CL is a parasitic capacitor such as a counter capacitor or a line capacitor, which is present in the plasma display. If a drive frequency is given by f0, power of f0xc3x97CLxc3x97V02 is generally wasted.
The low power driver device 600 is for recovering the wasted reactive power and operates as follows. When the output rises as shown in FIG. 1B, the pMOS 611 is turned on to form an equivalent circuit as shown in FIG. 2. The output rises to V0 by the resonant circuit composed of L1 and CL and at the moment, the pMOS 612 is turned on and thus the output is maintained at V0. On the other hand, when the output falls, the nMOS 621 is turned on to construct a resonant circuit as shown in FIG. 2. Thus, the output falls to 0 V. Also, the nMOS 622 is turned on and thus the output is maintained at 0 V. Such a series of operations is the operation of the resonant circuit and energy for charging CL is again recovered by CR. In addition, by this operation, a potential of CR is automatically maintained at V0/2.
When the low power driver device 600 is applied to the PDP device, for example, as shown in FIG. 3, an output terminal 601 is connected with a high voltage portion common power source terminal 501 of a driver IC 500 such as a scan driver circuit in the plasma display panel. The driver IC 500 supplies a high voltage V0 inputted from the high voltage portion common power source terminal 501 from output terminals 506a to 506x to predetermined electrodes in the plasma display panel through a selection portion 510. Reference symbol CL denotes a capacitor in the case where it is viewed from the output terminals 506a to 506x. The selection portion 510 is composed of a plurality of CMOS switch portions 511 to 51x. For example, the CMOS switch portion 511 connects a high voltage common wiring connected with the high voltage portion common power source terminal 501 with a ground by a serial connector made from the source drain path of a pMOS 511P and the source drain path of an nMOS 511N, and also connects a common connection point N21 with the output terminal 506a. Although the descriptions are omitted here, the other CMOS switch portions 512 to 51x have the same structure. Hereinafter, the CMOS switch portion 511 will be described as an example. With such a structure, at power recovery operation for recovering charges discharged from the load capacitor CL, the charges are recovered by the capacitor CR through the output terminal 506a, the common connection point N21, and the pMOS 511P in the driver IC 500. With this structure, when the driver IC is formed on a general silicon substrate with a self-isolation structure, an element cross sectional structure as shown in FIG. 4A is obtained (equivalent circuit is shown in FIG. 4B). Thus, a leak current Ir is produced through a P-type substrate 830 and an N-well parasitic bipolar transistor 891, which causes a reduction in power recovery efficiency. On the P-type substrate 830, P-type diffusion layers 836 and 832, N-type diffusion layers 831 and 833, and insulating layers 842 are formed. On the other hand, when it is formed on an SOI substrate with a trench isolation structure, an element cross sectional structure as shown in FIG. 5A is obtained (equivalent circuit is shown in FIG. 5B). Thus, there is an advantage in which all charges discharged from the load capacitor CL can be recovered by the capacitor CR. Therefore, in a high breakdown voltage semiconductor device including a display device driver IC, the SOI substrate is used as a chip substrate in many cases. On a silicon substrate 301, an insulating layer 302, and a semiconductor layer having P-type diffusion layers 353, N-type diffusion layers 356 and isolation trenches 315 are formed.
In addition to realizing lower consumption power of the display device, in order to progress miniaturization and decrease in thickness thereof, miniaturization and decrease in thickness of a semiconductor device to be used in large quantity as a driver circuit is essential. Also, with the driver circuit, mounting to a thin type package such as a TCP (tape carrier package) and coping with a bare chip assembly such as a flip chip assembly and are desirable. In mounting to the thin type package, the flip chip assembly, or the like, for example, as shown in FIGS. 16A and 16B, generally, a rear surface 806 (surface on which an element is not formed) of a semiconductor chip 800 is not connected with another conductor such as an island and thus becomes a floating state. Thus, when the SOI substrate is used as a chip substrate, generally, a conductive support substrate becomes a floating state. Therefore, if a conductive support substrate 801 becomes a floating state in the chip 800 using the SOI substrate as the chip substrate, the potential of the conductive support substrate 801 becomes unstable. Also, as disclosed in, for example, Japanese Patent No. 2654268 or Japanese Patent No. 3061020, an inverse breakdown voltage of a p-n junction formed in a semiconductor layer 803 on the SOI substrate is changed dependent on the potential of the conductive support substrate 801. Thus, if the conductive support substrate 801 becomes a floating state and its potential cannot be maintained at a suitable value, a problem such as the inverse breakdown voltage is greatly decreased is caused. Thus, the chip using the SOI substrate has been mounted on a package having an island such as a general lead frame. However, mounting the chip using the SOI substrate to the package including the TCP and an applying the chip using the same to the flip chip assembly, in which the rear surface of the chip in which an element is not formed becomes a floating state and thus the potential of the rear surface cannot be maintained, cannot be made.
As one method for solving this problem, a semiconductor device having a structure such as a predetermined potential can be provided from the side of the semiconductor layer in which an element is formed to the conductive support substrate even in the case where the SOI substrate is used as the chip substrate, is disclosed in Japanese Patent Application Laid-open No. Hei. 6-244239, Japanese Patent Application Laid-open No. Hei. 11-354631, or Japanese Patent Application Laid-open No. 2000-156408.
FIG. 6 is a partially cross sectional view enlarging a main portion (vicinity of a scribing end surface 1611) in the case where the flip chip assembly is made for the semiconductor device disclosed in Japanese Patent Application Laid-open No. Hei. 6-244239. With reference to FIG. 6, a semiconductor layer 1603 of the semiconductor device is insulated from a semiconductor substrate 1601 by an intermediate insulating film 1602. However, a short circuit conductor 1610 provided on the side surface of a concave portion 1609 that reaches the semiconductor substrate 1601 is short-circuited with the semiconductor substrate 1601 and a peripheral region portion 1603b. Thus, the semiconductor substrate 1601 is provided with the same potential as the peripheral region portion 1603b. The peripheral region portion 1603b is provided with a potential from a wiring substrate 1608 through, for example, a bump 1607 equal to an element forming region portion. That is, the potential can be provided from the front surface side of the semiconductor layer 1603 in which an element is formed to the semiconductor substrate 1601. A silicon oxide film 1612, a silicon nitride film 1613, an aluminum electrode 1614, a ground potential line 1615, an opening for a bump 1607 are formed as shown in FIG. 6.
FIG. 7 is a main portion cross sectional view of the semiconductor device disclosed in the Japanese Patent Application Laid-open No. Hei. 11-354631. With reference to FIG. 7, this semiconductor device is composed of an SOI substrate with which an Nxe2x88x92-type semiconductor layer 1742 is provided through a silicon oxide film 1743 on an N-type Si semiconductor support substrate 1741 including an N+-type semiconductor layer 1741b disposed on the surface layer of a silicon substrate 1741a. With respect to an element forming region 1730 of the semiconductor layer 1742, in which a high breakdown voltage MOSFET element is formed, an N+-type semiconductor region 1744 is provided in the surface layer and a P-type semiconductor region 1745 is provided at a depth to the silicon oxide film 1743 so as to circularly surround the N+-type semiconductor region 1744 at a predetermined distance. In the surface layer of the P-type semiconductor layer 1745, an N+-type semiconductor region 1753 is provided in a position at a predetermined distance as a channel length from a PN junction between the semiconductor layer 1742 and the P-type semiconductor region 1745 and a P+-type semiconductor region 1754 is provided adjacent to the N+-type semiconductor region 1753. A drain electrode 1746 is provided for the N+-type semiconductor region 1744 with ohmic contact. Also, a source electrode 1747 is provided for the N+-type semiconductor region 1753 and the P+-type semiconductor region 1754 with ohmic contact. An isolation layer 1749 that reaches the silicon oxide film 1743 and isolates the semiconductor layer 1742 into a plurality of regions is provided on the semiconductor layer 1742. An element forming region 1730 is surrounded by the isolation layer 1749. A conductive layer 1752 which reaches the semiconductor support substrate 1741 through the silicon oxide film 1743 and is made of N+-type polysilicon, is provided in a substrate potential lead region 1740 of the semiconductor layer 1742 isolated from the element forming region 1730. Note that, when the surface layer of the semiconductor support substrate 1741 is a P+-type, a conductive layer made of P+-type polysilicon is provided. A substrate potential keeping electrode 1748 is connected on a conductive layer 1752. Although not shown, the substrate potential keeping electrode 1748 is connected therewith at the same potential as the source electrode 1747. An insulating film 1751 is provided in the surface of the semiconductor layer 1742 except for positions in which the drain electrode 1746, the source electrode 1747, and the substrate potential keeping electrode 1748 are connected. A gate electrode 1756 is provided in the insulating film 1751 in a position between the semiconductor layer 1742 and the N+-type semiconductor region 1753 on the P-type semiconductor layer 1745 through a gate oxide film 1755 included in the insulating film 1751.
The operation of the N-channel high breakdown voltage MOSFET in the semiconductor device having the above structure is as follows. When the source electrode 1747 and the substrate potential keeping electrode 1748 is kept to be 0 V and then a positive voltage is applied to the drain electrode 1746 while the gate electrode 1756 is in an off control state, a depletion layer is extended from the PN junction between the semiconductor layer 1742 and the P-type semiconductor region 1745 to the side of the semiconductor layer 1742. At this time, the entire semiconductor support substrate 1741 becomes 0 V from the substrate potential keeping electrode 1748 through the conductive layer 1752 and functions as a field plate through the silicon oxide film 1743. Thus, in addition to the above depletion layer, a depletion layer is extended in the direction from the interface between the semiconductor layer 1742 and the silicon oxide film 1743 toward the surface of the semiconductor layer 1742. Therefore, the former depletion is easy to extend by this influence and an electric field in the PN junction between the semiconductor layer 1742 and the P-type semiconductor region 1745 is relaxed.
As described above, the potential of the semiconductor support substrate 1741 as the SOI substrate is maintained at the potential of the source electrode 1747 through the substrate potential keeping electrode 1748 provided in the surface. Thus, with respect to the chip using the SOI substrate as the chip substrate, without providing the rear surface of the SOI substrate with the electrode, mounting of the high breakdown voltage MOSFET element is allowed utilizing a surface electric field relaxation effect in the element forming region 1730 in which the MOSFET element is formed. And, (1) mounting of a semiconductor device chip having the high breakdown voltage MOSFET on a BGA (ball grid array) as a surface mount type IC package or a CSP (chip size package) is allowed and (2) use of an insulating paste for reducing a die bonding cost is allowed in the case where the chip is connected by wire bonding or die bonding.
FIG. 8 is a cross sectional structure view of the semiconductor device disclosed in Japanese Patent Application Laid-open No. 2000-156408. With reference to FIG. 8, in this semiconductor device, a first insulating oxide film 1802 is formed on a semiconductor support substrate 1801 made of P-type silicon, an SOI layer 1803 made of P-type silicon is provided on the first insulating oxide film 1802, and semiconductor elements not shown are formed in the SOI layer 1803.
Also, a hole 1804 which penetrates the SOI layer 1803 and the first insulating oxide film 1802 and reaches the surface of the semiconductor support substrate 1801 is formed in a predetermined position. The side surface and the bottom surface of the hole 1804 are filled with a second insulating oxide film 1806 to form an element isolation region, and thus the semiconductor elements formed on the SOI layer 1803 are electrically isolated. Further, a hole 1805 that penetrates the SOI layer 1803 and the first insulating oxide film 1802 and reaches the surface of the semiconductor support substrate 1801 is formed in a predetermined position. The side surface and the bottom surface of the hole 1805 are filled with P-type polysilicon to form a conductor layer 1807 for providing the semiconductor support substrate 1801 with a potential.
A third insulating oxide film 1808 in which a hole 1809 reaching the conductor layer 1807 is formed is deposited on the SOI layer 1803. Further, a wiring aluminum electrode 1810 is formed on the third insulating oxide film 1808. The electrode 1810 simultaneously fills the hole 1809 and electrically connects with the conductor layer 1807. By such a structure, a predetermined potential can be provided from the electrode 1810 formed in the surface to the semiconductor support substrate 1801.
In Japanese Patent Application Laid-open No. Hei. 6-244239 and Japanese Patent Application Laid-open No. Hei. 11-345631, a potential can be provided from the surface of the semiconductor layer forming an element in the SOI substrate to the conductive support substrate and the potential of the conductive support substrate can be kept without providing the rear surface of the chip with the electrode. However, there is a problem in which the structure is complicated and the addition of a step is required. For example, Japanese Patent Application Laid-open No. Hei. 6-244239, in order to provide a potential from the surface of the semiconductor layer to the conductive support substrate, it is necessary to add at least a step of removing the semiconductor layer of the scribe region and the intermediate insulating layer for insulating the semiconductor layer from the conductive support substrate to form an concave trench and a step of depositing aluminum to form a short circuit conductor in the side walls of the concave trench. Also, in Japanese Patent Application Laid-open No. Hei. 11-345631 and Japanese Patent Application Laid-open No. 2000-156408, it is necessary to add a step of providing a connection hole which penetrates the insulating layer from the surface of the semiconductor layer forming an element in the SOI substrate and reaches the conductive support substrate and a step of filling the connection hole with polycrystalline silicon. Note that the connection hole and the element isolation trench can be simultaneously formed. However, in this case, a filling material for the connection hole is different from that for the element isolation trench. Thus, although the detail description is omitted here, it is necessary to add another step and degrees in the addition of the step are not greatly different.
An illustrative, non-limiting embodiment of the present invention provides a semiconductor device in which the potential of the conductive support substrate can be kept to be a predetermined potential while the SOI substrate is used as the chip substrate, without adding a new step and providing a rear electrode. Thus, the thinness of the high breakdown voltage semiconductor device and the support to the flip chip assembly are allowed and the improvement of power recovery efficiency of the flat type display device can be compatible with the miniaturization and the thinness of the display device.
The present invention is based on the following findings from various experiments during the development progress of the above thin type and high breakdown voltage semiconductor device, but is not limited thereto. That is, even in the case where the SOI substrate is used as the chip substrate, when the chips are separated into individual items by dicing, an electrical continuity path is caused in an insulating layer of the side end surface of the chip, and thus a current path is formed between the peripheral portion of a semiconductor layer and a conductive support substrate. When at least the peripheral portion of the semiconductor layer and the conductive support substrate are set to be the same conductivity type, even if the rear surface of the conductive support substrate is not connected with another conductive material, the conductive support substrate can be set to be the same potential as the peripheral region of the semiconductor layer. The present invention is adapted to solve the above problems based on the findings.
Thus, one illustrative, non-limiting embodiment of a semiconductor device of the present invention has a chip in which a desired element is formed in a semiconductor layer of an SOI (silicon on insulator) substrate having a structure in which the semiconductor layer is laminated on a conductive support substrate through an insulating layer, and is characterized in that, the chip includes, in the semiconductor layer, a plurality of isolation trenches filled with an insulating material and reaching to the insulating layer, and a plurality of element forming regions in which the desired element is formed by surrounding its periphery by the isolation trenches, and the chip further includes a peripheral region connection wiring for connecting a contact region provided in a predetermined position of a peripheral region, which is not surrounded by any one of the isolation trenches, with an electrode having a predetermined potential within at least one of the element forming regions.
In this case, one of the isolation trenches may be an outermost isolation trench that surrounds all the element forming regions. Also, the chip can further include a second element forming region in which the desired element is formed by surrounding its periphery by at least double of the isolation trenches.
Also, when the chip includes a low voltage operation circuit which operates with a power source voltage of, for example, 10 V or lower, and a high voltage operation circuit which operates with 20 V or higher, it is desirable that an element composing at least the high voltage operation circuit is formed within the second element forming region.
Also, the chip can include a driver circuit portion of a display device and further include a recovery electrode, which is connected at least with the driver circuit portion in the chip and a power recovery circuit. Also, the display device can be selected from a plurality of flat type display devices including a plasma display device and an electroluminescence display device.
Also, when the conductive support substrate is one conductivity type semiconductor substrate, it is desirable that the semiconductor layer that becomes at least the peripheral region of the chip, has one conductivity type.
Also, when the chip is mounted into a package and assembled, it may be made with a state so that a rear surface of the chip, in which the conductive support substrate is exposed, is not brought into contact with another conductive material including an island in which the chip is mounted.
Also, one illustrative, non-limiting embodiment of a method of manufacturing the semiconductor device includes: a first step of preparing an SOI wafer in which one conductivity type semiconductor layer is formed on one conductivity type semiconductor substrate through an insulating layer; a second step of opening an isolation trench that reaches the insulating layer in the one conductivity type semiconductor layer, and filling the isolation trench with a predetermined insulating material to divide a plurality of element forming regions, and forming an outermost isolation trench surrounding all the element forming regions in the same chip; a third step of forming a desired element in the plurality of element forming regions divided by the isolation trench; a fourth step of, in each of a plurality of chips arranged in an alignment state on the wafer through a scribe region, forming a chip interconnection wiring including a peripheral region connection wiring connected with an electrode having a predetermined potential in the element forming region through a contact hole provided in a predetermined position of a peripheral region outside the outermost isolation trench; and a fifth step of dicing the scribe region to separate the plurality of chips into individual items.